`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:21:54 02/25/2014
// Design Name:   vga
// Module Name:   C:/Xilinx/14.7/predator-vision-73e76af01d2e/vga_tb.v
// Project Name:  pseudo_with_clocking
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: vga
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module vga_tb;

	// Inputs
	reg pixelClock;
	reg [7:0] Red_in;
	reg [7:0] Green_in;
	reg [7:0] Blue_in;

	// Outputs
	wire [7:0] Red;
	wire [7:0] Green;
	wire [7:0] Blue;
	wire hSync;
	wire vSync;
	wire blank;

	// Instantiate the Unit Under Test (UUT)
	vga uut (
		.pixelClock(pixelClock), 
		.Red_in(Red_in), 
		.Green_in(Green_in), 
		.Blue_in(Blue_in), 
		.Red(Red), 
		.Green(Green), 
		.Blue(Blue), 
		.hSync(hSync), 
		.vSync(vSync), 
		.blank(blank)
	);

	initial begin
		// Initialize Inputs
		pixelClock = 0;
		Red_in = 0;
		Green_in = 0;
		Blue_in = 0;
	end
      	always begin
			#5 pixelClock = ~pixelClock;
	end
		
	initial begin
		#100
		Red_in <= 8'd111;
		Green_in <= 8'd111;
		Blue_in <= 8'd111;
		$monitor("Red = %d , Green = %d, Blue = %d", Red, Green, Blue ); 
		#10
		Red_in<= 8'd101;
		Green_in <= 8'd101;
		Blue_in <= 8'd101;
		$monitor("Red = %d , Green = %d, Blue = %d", Red, Green, Blue ); 
	
		#200 $finish;
	end
endmodule

